Apparatus and method of implementing breq routing to allow functionality with 2 way or 4 way processors
作者： Peter M. Arnold , Ross V. La Fetra
DOI:
关键词: Embedded system 、 Back-side bus 、 System bus 、 Local bus 、 Bus 、 Control bus 、 Computer hardware 、 Bus network 、 Address bus 、 Computer science 、 IEBus
摘要: An apparatus for implementing bus request routing to allow functionality with 2 way or 4 processors, includes a configured provide routing; and route switching stage coupled the select first configuration if two processors are bus. The is also second more that determines A logic block may be used determine required based on detected processor population. method of changing includes: detecting dual arrangement multi-processor bus; selecting
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