Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications

摘要: For real-time applications, there are several factors (time, cost, power) that moving security considerations from a function centric perspective into system architecture (hardware/software) design issue. Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address issues. The AES algorithm specifies three key sizes: 128, 192 256 bits offering different levels of security. To deal with the amount application intensive computation given by mechanisms, we define develop QoSS (Quality Security Service) model for reconfigurable processor. has been designed implemented achieve flexible trade-off between overheads caused services performance. proposed can provide up 12 block cipher schemes within reasonable hardware cost. We envisage vector fully functional request include service range mechanisms. Our unified run both original extended (QoSS-AES). A novel on-the-fly encryption/ decryption also 128-, 192-, 256-bit keys. The performance processor analyzed an MPEG4 video compression standard. results revealed QoSS-AES well suited high communication low latencies. In our implementation based on Xilinx Virtex FPGAs, speed/area/power these processors shown compare favorably other known FPGA implementations.