Enhanced computer processor and memory management architecture

摘要: Disclosed in some examples is an improved computing architecture, which includes multiple processor cores and I/O devices communicating with memory banks using a High Speed Interconnect Unit (HSU). The HSU quickly routes (e.g., one clock cycle) access request from device or core to particular bank over of number independent routes, each route servicing bank. routing based upon the values preselected bit positions (“preselected bits”) requested address, bits being chosen so as maximize distribution accesses entire system across all available (and by extension distributing routes).