Datamining for yield
作者： Raymond Van Roijen , Jeffery B. Maxson , Michael Brodfuehrer , Bruce Dyer , Colleen Meagher
DOI: 10.1109/ASMC.2017.7969251
关键词: Data mining 、 Materials science 、 Wafer 、 Process (computing) 、 Processes of change 、 Yield (engineering) 、 Root cause 、 Signal 、 Metal gate 、 Deposition (phase transition)
摘要: A small but persistent signal in wafer slot order was observed at functional test, affecting logic yield. Through Randomization several operations the route a process step within high-k metal gate formation suspected to be causing degrade, conventional approaches did not reveal root cause. By combining datamining with thorough analysis of sector and electrical data we identified defect mechanism exacerbated by delay between polysilicon deposition. applying change, addressed issue achieved yield improvement.
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