Virtual address translator

摘要: A virtual address translator comprises a content addressed memory and word memory. task name subsegment number from supplied by processor are employed as key to search read out descriptor if the is matched. The includes an absolute base which added deflection field obtain address. applied permit transfer of between may present any one several names depending upon whether reference made for instruction or data processor, I/O connected processor. Bounds, residency access privileges checked using descriptor. If reveals that desired not in memory, obtains then generates provided with circuits generating values indicate efficiency its operation. Controls selecting widths fields addresses received