Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP

作者: Uwe Vehlies

DOI: 10.1155/1995/76861

关键词: AlgorithmElectronic design automationComputationComputer scienceParallel computingMassively parallel systemsTransformation (function)Digital signal processing algorithmsHardware description languageVector processorDesign flow

摘要: A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions hardware description language. The itself divided manageable steps and implemented CAD-tool DECOMP which allows exploration different short time. With presented data independent can be mapped onto architectures. To allow this, known mapping methodology extended handle inhomogeneous dependence graphs with nonregular dependences. implementation an important step towards automation massively parallel systems.

参考文章(18)
Wade L. Hennessey, Common Lisp ,(1989)
Uwe Vehlies, The derivation of dependence graphs from PASCAL programs for array processor design Proceedings of the international workshop on Algorithms and parallel VLSI architectures II. pp. 371- 376 ,(1992)
P. Pirsch, VLSI Architectures for Digital Video Signal Processing Computer Systems and Software Engineering. pp. 65- 99 ,(1992) , 10.1007/978-1-4615-3506-5_3
A. Munzner, P. Pirsch, BADGE-building block adviser and generator international symposium on circuits and systems. pp. 1887- 1890 ,(1989) , 10.1109/ISCAS.1989.100737
J. Fortes, K. Fu, B. Wah, Systematic approaches to the design of algorithmically specified systolic arrays international conference on acoustics, speech, and signal processing. ,vol. 10, pp. 300- 303 ,(1985) , 10.1109/ICASSP.1985.1168513
R. Camposano, From behavior to structure: high-level synthesis IEEE Design & Test of Computers. ,vol. 7, pp. 8- 19 ,(1990) , 10.1109/54.60603
A. Berlin, D. Weise, Compiling scientific code using partial evaluation IEEE Computer. ,vol. 23, pp. 25- 37 ,(1990) , 10.1109/2.62091
D.I. Moldovan, On the design of algorithms for VLSI systolic arrays Proceedings of the IEEE. ,vol. 71, pp. 113- 120 ,(1983) , 10.1109/PROC.1983.12532
Patrice Quinton, Automatic synthesis of systolic arrays from uniform recurrent equations international symposium on computer architecture. ,vol. 12, pp. 208- 214 ,(1984) , 10.1145/773453.808184