作者: Paola Redivo , Guido Ghisio , Maurizio Catena
DOI:
关键词: Interval (graph theory) 、 Computer hardware 、 Transfer (computing) 、 Combinatorics 、 Signal edge 、 Computer science 、 Enhanced Data Rates for GSM Evolution 、 Signal
摘要: The device includes first and second counters (S; D) the changes of output data (s₁...s n ; d₁...d ) which correspond to leading edges (a s trailing d respectively signal (A) whose pulses are be counted, control devices (FF, M) for detecting level when a switching edge (e), defines end counting period, occurs in (B). adapted transfer memory register (R) by counter (S) if is at "high" (B) (D) "low"