Efficient genetic based topological mapping using analytical models for on-chip networks

摘要: Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens hundreds IP cores. Higher scalability (compared traditional shared bus and point-to-point interconnects), throughput, reliability among most important advantages of NoCs. Moreover, NoCs can well match current CAD methodologies mainly relying on modular reusable structures regularity structural pattern. However, since resource-limited, determining how distribute application load over limited resources (e.g. switches, buffers, virtual channels, wires) order improve metrics interest satisfy requirements becomes a challenging research issue known as topological mapping problem. This paper introduces strategy for direct networks. The Multi-Objective Genetic Algorithm (MOGA) is used obtain optimal Pareto-front solutions an arbitrary network topology using deadlock-free routing algorithm. Considered cost functions latency power consumption which accurately estimated through two accurate analytical models. Before proposed models our MOGA method, we validate them extensive simulation experiments, compare their accuracy some already literature. We then quantitatively qualitatively model based method other methods: genetic-based heuristic. Experimental evaluations real workloads confirm that cost-efficient be powerful tool NoC design space exploration. Compared strategies, mechanism has following advantages: (1) it greatly shortens period by fast predictions; (2) give set solutions, MOGA, terms including, at least one performance-optimal power-optimal, intermediate solutions; (3) its runtime reduced best generation size benchmark.