Parallel requestor priority determination and requestor address matching in a cache memory system

作者: James Herman Scheuneman

DOI:

关键词: Cache algorithmsMemory mapCache-only memory architectureComputer hardwarePage cacheCache coloringCacheUniform memory accessCache pollutionComputer networkComputer science

摘要: A method of and an apparatus for performing, in a Cache memory system, the Priority determination what Requestor, R Requestors, is to be granted priority by Network while simultaneously comparing, parallel, all Requestors' addresses Match condition memories. The system incorporates separate or associative each which memories comprised Address Buffer Search memory, associated are stored, Data Associated data that with stored. Thus, Request signals from requesting Requestors being coupled single Network, Requestor separately memory. As require approximately same time complete, parallel operation thereof substantially reduces access either Main

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Ronald E. Lange, Matthew A. Diethelm, Phillip C. Ishmael, Cache memory store in a processor of a data processing system ,(1974)