Digital multi-channel counter method and apparatus to reduce counting hardware

摘要: In systems requiring multiple identical digital correlators the original m-bit counter for each correlator can be replaced by an n-bit multi-channel counter. The most significant bit of is sampled every 2n-1 clock cycles and results are stored in dual port memory. Stored input samples converted into a series binary words which multiplexed to one two signal outputs. memory allows current from counters written on A, while previously time read output B. This design not only reduces number parts needed but also buffers so many appear same computer bus. addition, maximum delay between sampling any greatly reduced.