Switch-Level Delay Models for Digital MOS VLSI

摘要: This paper presents fast, simple, and relatively accurate delay models for large digital MOS circuits. Delay modeling is organized around chains of switches nodes called stages, instead logic gates. The use stages permits both gates pass transistor arrays to be handled in a uniform fashion. Three are presented, ranging from an RC model that typically errs by 25% slope-based whose estimates within 10% SPICE's estimates. slope parameterized terms the ratio between slopes stage's input output waveforms. All have been implemented Crystal timing analyzer. They evaluated comparing their SPICE, using dozen critical paths two VLSI designs.