作者: Young Hoon Lee , Ying Zhang
DOI:
关键词: Structural engineering 、 Amorphous solid 、 Silicon 、 Copper interconnect 、 Insulation layer 、 Semiconductor 、 Materials science 、 Interconnection 、 Insulator (electricity) 、 Optoelectronics
摘要: In a dual-damascene processes for multi level interconnection method forming trenches and vias in the inter-insulation is accomplished without etching out layer. A thick sacrificial layer first deposited reversed etched to form pillars 64 bridges 72 trenches. The can be any material (insulator, semiconductor, or metal), provided it easily patterned selectively removed later over inter insulator Thereafter low-k around bridges. It these that are away leaving behind An advantage of invention replaces difficult RIE process with much easier preferred embodiment, silicon film, either amorphous polycrystalline, used as