Edge-missing detector structure
作者： Chin-Long Wey , Chun-Ming Huang , Ting Hsu Chien , Ying-Zong Juang , Chi Sheng Lin
DOI:
关键词: Physics 、 Electrical engineering 、 Logic gate 、 Phase-locked loop 、 Phase detector characteristic 、 Clock signal 、 Topology 、 Detector 、 Phase detector 、 Signal 、 Phase (waves)
摘要: An edge-missing detector structure includes a first detector, delay unit, logic gate, second and gate. After being input separately into the structure, reference signal clock are detected by detectors then subjected to cycle suppression gates, respectively, so as generate which present phase difference less than 2π. Moreover, generates compensative current corresponding number of occurrences suppression. Thus, phase-locked loop (PLL) using can avoid slip problems achieve fast acquisition lock.
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