M7: Oracle's Next-Generation Sparc Processor
作者： Kathirgamar Aingaran , Sumti Jairath , Georgios Konstadinidis , Serena Leung , Paul Loewenstein
DOI: 10.1109/MM.2015.35
关键词: Shared memory 、 CPU cache 、 Parallel computing 、 Pipeline burst cache 、 Memory hierarchy 、 Multiprocessing 、 Computer science 、 Non-uniform memory access 、 Memory bandwidth 、 Multi-core processor 、 Garbage collection 、 Cache 、 Operating system 、 Memory management 、 Uniform memory access
摘要: The Oracle Sparc M7 processor more than triples the throughput of M6 processor, while increasing per-thread performance, power efficiency, and I/O bandwidth. contains 32 8-thread, dual-issue, out-of-order cores. To minimize L3 cache hit latency, features a partitioned cache, with novel on-chip network for communication between partitions, coherence control, memory. Memory bandwidth is 3 times that processor. On-chip accelerators providing query filtering decompression can provide another order magnitude performance increase these tasks. keeps consumption at minimum through multiple power-saving techniques. scales to 32-processor shared memory multiprocessing systems (SMPs). Coherent also supported SMPs in cluster. Such cluster robust against both SMP failure. Application data integrity guards pointer-related software vulnerabilities without slowing Fine-grained migration supports concurrent garbage collection.
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computer.org参考文章(7)
Penny Li, Jinuk Luke Shin, Georgios Konstadinidis, Francis Schumacher, Venkat Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, 4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor international solid-state circuits conference. pp. 1- 3 ,(2015) , 10.1109/ISSCC.2015.7062931
Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King Yen, Venkat Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin, Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). pp. 373- 376 ,(2014) , 10.1109/ASSCC.2014.7008938
John Feehrer, Sumti Jairath, Paul Loewenstein, Ram Sivaramakrishnan, David Smentek, Sebastian Turullols, Ali Vahidsafa, The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets IEEE Micro. ,vol. 33, pp. 48- 57 ,(2013) , 10.1109/MM.2013.49
Venkat Krishnaswamy, Jeffrey Brooks, Georgios Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang, 4.3 Fine-grained adaptive power management of the SPARC M7 processor international solid-state circuits conference. pp. 1- 3 ,(2015) , 10.1109/ISSCC.2015.7062932
Thomas Wicki, Jurgen Schulz, Bixby: The scalability and coherence directory ASIC in Oracle's highly scalable enterprise systems ieee hot chips symposium. pp. 1- 34 ,(2013) , 10.1109/HOTCHIPS.2013.7478325
Ram Sivaramakrishnan, Sumti Jairath, Next generation SPARC processor cache hierarchy ieee hot chips symposium. pp. 1- 28 ,(2014) , 10.1109/HOTCHIPS.2014.7478828
Stephen Phillips, M7: Next generation SPARC ieee hot chips symposium. pp. 1- 27 ,(2014) , 10.1109/HOTCHIPS.2014.7478832