Hardware support for superpage coalescing

摘要: A method of assigning virtual memory to physical in a data processing system allocates set contiguous pages for new page mapping, instructs the controller move according and then allows access using mapping while is still copying pages. The can use table which temporarily stores entries old addresses, releases as each entry completed. translation lookaside buffer (TLB) processor cores are updated addresses prior completion by controller. invention be extended non-uniform array (NUMA) systems. For systems with cache memory, any affected modifying its address tag mapping. This modification may limited dirty coherency state. further relocate based on changed congruence class modified tag.