Device for testing clock synchronization correction value of time-triggered Ethernet by capturing protocol control frame
作者： Tang Xuegan , Kong Yunwen , Li Qiao
DOI:
关键词: Cyclic redundancy check 、 Telecommunications link 、 Computer hardware 、 Ethernet 、 Fault injection 、 Frame (networking) 、 Computer science 、 Clock synchronization 、 Computer data storage 、 Multiplexing
摘要: The invention discloses a device for testing clock synchronization correction value of time-triggered Ethernet (TTE) by capturing protocol control frame (PCF). comprises transmitting and receiving modules (1 6), type identification (2 7), transparent field processing (3 8), cyclic redundancy check code calculation (4 9), data multiplexing (5 10), module (11), storage (12), bearing content addition (13) and/or fault injection (14). PCF-time disclosed the can obtain distributed an SM under precondition not rebuilding software hardware CM through observing uplink downlink PCF which belong to same integrated cycle in full duplex link, inject tampering TC (Transparent Clock) domain PCF.
lens.org 参考文章(4)
Janakiraman Senthilnathan, Matthew H. Harper, Synchronizing data transmission over wireless networks ,(2006)
Xiong Huagang, Lan Jie, Li Qiao, Wang Mengdi, Method suitable for monitoring inside compression master and capable of improving clock synchronization fault tolerance ,(2014)
Wang Tong, Wang Mengdi, Xiong Huagang, He Feng, Simulation system of simulating switched Ethernet clock synchronization ,(2014)
Yangfeng Wang, Sheng You, Xiaomin Yang, Diqiang Zhang, Yonghua Li, Data transmission method and device ,(2013)