Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Synchronization

摘要: Clock synchronization is one of the basic services in a distributed network as it enables palette services, such synchronized measurements and actions, or time-based access to shared communication media. The IEEE 1588 standard defines precision time protocol (PTP) that capable synchronizing multiple slave clocks master by means event messages. Supported recent advances hardware timestamping, PTP devices are ready for achieving accuracies subnanosecond range. accuracy practical systems is, however, often bounded inability determine compensate asymmetric line delays leading unresolvable clock offsets. Although version 2008 able known asymmetry, no specific measures estimate asymmetry defined standard. In this paper, we present solution 100Base-TX networks based on swapping highly accurate timestamping. When presented approach used within startup procedure an Ethernet link, offsets can be minimized while operation not impaired. We show FPGA-based prototype system our reduce offset from nanoseconds below 120 ps.