Reproducible user-level simulation of multi-threaded workloads

摘要: As the complexity of processors increases, it becomes harder for designers to understand non-trivial and many times non-intuitive interactions among micro-architecture internal structures. Understanding these is important because helps pinpoint bottlenecks, enabling reason about sources performance loss improve their next generation processors. To help in current and, more importantly, future designs, make heavy use computer architecture detailed simulation. These simulators model behavior processor on a per-cycle basis, allowing look at very trade-offs. Building maintaining large complicated task. In addition, recent trends designing micro-architectures with multiple cores same chip brings new challenges that affect way simulation results should be compared. This dissertation focuses techniques build maintain simulators, as well architects evaluate design choices using Existing user-level require manual hand coding emulation each every possible system effect (e.g., call, interrupt, DMA transfer) can impact application's execution. Developing such an emulator given operating tedious exercise, also costly support newer versions system. Furthermore, porting completely different might involve building all together from scratch. The first contribution this technique automatically capture effects application. are captured logs then used guide By proposed technique, implementing greatly reduced. guarantees deterministic uni-processor systems. As multi-core become main stream, address efficient multi-threaded workloads needed. Simulation systems suffer non-determinism across runs configurations. If execution paths between two benchmark, input, too different, cannot compare other contributions focus efficiently collect checkpoints workloads. It extends previous Using checkpoints, deterministic. stalls would not naturally occur proposes allow one accurately configurations presence stalls.