Making good points

摘要: Field-programmable gate arrays (FPGAs) commonly implement system architectures composed from soft-core configurable components, such as a cache with size or associativity, processor datapath units, network-on-chip connecting dozens of processors. Configurable components increasingly exist even on pre-fabricated platforms. Tuning to the particular application running architecture and design constraints represents challenging task often left designer. Knowledge Pareto-optimal points for applications can be benefit designers seeking make appropriate tradeoffs given constraints. Previous methods generating Pareto required extensive knowledge an architecture's parameter interdependencies, used simplistic approach that failed find many parameters, randomized search algorithms may have long runtimes. We introduce algorithm finding points, based statistically rigorous derived Design Experiments paradigm extended purpose points. The resulting DoE-based point Generator, DPG, finds thorough while 3 times faster than algorithms, without requiring designer interdependencies--in fact, determines those interdependencies automatically, representing added bonus. demonstrate DPG Platune's processor-bus-cache system-on-chip, Noxim's network-on-chip, Microblaze FPGA processor.