A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation
作者： T. Kobayashi , K. Nogami , T. Shirotori , Y. Fujimoto , Y. Biwaki
DOI: 10.1109/4.98976
关键词: Parallel computing 、 Cache 、 Snoopy cache 、 CPU cache 、 CMOS 、 Non-uniform memory access 、 MESIF protocol 、 Kilobyte 、 Engineering 、 Write-once
摘要: A 64-kbyte snoopy cache memory was developed. The modified double word-line architecture with buffers resulted in a large-size and time-multiplex snoop operation by the pseudo-two-port method single-port cell. flexible expandability achieved cascading multiple memories. device successfully implemented 1.0- mu m double-polysilicon double-metal CMOS technology. Low-power sense amplifiers comparators limited power dissipation to 0.5 W at 40 MHz. >
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