Delay locked loop for use in semiconductor memory device
作者： Seong-Hoon Lee
DOI:
关键词: Phase-locked loop 、 Synchronous circuit 、 Round-trip delay time 、 Delay-locked loop 、 Group delay and phase delay 、 Shift register 、 Self-clocking signal 、 Mathematics 、 Delay line oscillator 、 Control theory
摘要: A delay locked loop (DLL) is disclosed which has finer adjustability. The generally includes: a first shift register (330) for controlling amount of an internal clock in response to shift-right signal and shift-left signal, line (340) delaying the according output register, wherein includes plurality units, each unit having amount; second (350) are outputted from register; (360) by predetermined larger than amount.
lens.org 参考文章(8)
Syuji Matsuo, Koichi Kitamura, Itsurou Taniyoshi, Tetsuo Saitoh, Digital phase locked loop having coarse and fine stepsize variable delay lines ,(1995)
Hea-Suk Jung, Delay locked loop having fast locking time ,(2000)
Masao Taguchi, Ayako Kitamoto, Masato Matsumiya, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Yoshinori Okajima, Toshikazu Nakamura, Kuninori Kawabata, Masato Takita, Satoshi Eto, Koichi Nishimura, Variable delay circuit and semiconductor integrated circuit device ,(2000)
Deog-Kyoon Jeong, Data receiving method and circuit of digital communication system ,(1995)
Seung-Hun Lee, Digital delay locked loop circuit using synchronous delay line ,(1996)
Tony Susanto, David S. Trager, David J. Knapp, Phase-locked loop with protected output during instances when the phase-locked loop is unlocked ,(1997)
Yukihiko Shimazu, Toshio Kishi, Digital delay circuit and digital PLL circuit with first and second delay units ,(1997)
Jean-Marc Patenaude, Ian Kyles, Continuously adjustable delay circuit ,(1998)