Analog phase locked loop

作者: Jan H. Erkku , Peter Gillingham

DOI:

关键词: Pulse (signal processing)DetectorPhase-locked loopAnalog signalVoltage-controlled oscillatorPhase (waves)SynchronizingDigital signalElectronic engineeringComputer science

摘要: A phase locked loop for synchronizing a local digital signal with an incoming data is described. Parallel and frequency detectors compare the signals generate control pulse controlling of voltage controlled oscillator which generates signal. Logic circuitry included in both adjusting generated event detection elongated widths signal, indicating one either absence or bipolar violation are ASI encoded. The characterized by quick pull-in time, large range, accurate clocking low cost.

参考文章(7)
Kazuya Toyomaki, Kazuo Hikawa, Hiroyuki Yamazaki, Clock generator for digital demodulators ,(1985)
Masayuki Ikeda, Variable frequency oscillator ,(1991)
Kazuya Toyomaki, Kazuo Hikawa, Hiroyuki Yamazaki, Sync responsive clock generator for digital demodulators ,(1985)
James G. Boone, Digital phase lock circuit ,(1978)
Peter H Halpern, Data synchronizing systems ,(1974)