An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs

摘要: Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU devices low capacity order to focus on operations does not have sufficient performance detection access. In contrast, field-programmable gate array (FPGA) can apply devices. By using the FPGA, able use parallel processing, super pipeline that independent of word width size. However, FPGA has problem delay times arithmetic circuits longer than an application specific integrated circuit (ASIC) or CPU. this paper, authors propose architecture ASIC-FPGA co-design addressing problem. evaluate architecture, adders enhanced by evaluated. As result, it shown with solved.