A re-configurable pipeline ADC architecture with built-in self-test techniques

摘要: High-performance analog and mixed-signal integrated circuits are integral parts of today's future networking communication systems. The main challenge facing the semiconductor industry is ability to economically produce these ICs. This translates, in part, into need efficiently evaluate performance such ICs during manufacturing (production testing) come up with dynamic architectures that enable be maximized later when they're operating field. On evaluation side, this dissertation deals concept Built-In-Self-Test (BIST) allow efficient economical certain classes high-performance circuits. architecture pipeline ADCs use BIST dynamically, production testing or field, re-configure them better performing In system proposed, test signal generated on-chip by sigma-delta modulation techniques. ADC measured a digital narrow-band filter. When used on wafer level, significant time thus cost can saved. A re-configurable improve proposed. Based measurements, best configuration chosen from collection possible configurations. basic algorithm applied many proposed grouping cuts down number permutation thousands 18 for 9-bit allowing method "real" applications. To validate developments dissertation, 40MS/s was designed implemented TSMC's 0.25pm single-poly CMOS process. includes fully differential folded-cascode gain-boosting operational amplifier high gain unity-