A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate
作者： Vandana Shukla , O. P. Singh , G. R. Mishra , R. K. Tiwari
DOI: 10.4018/IJBDCN.2015010104
关键词: Digital electronics 、 Electronic engineering 、 Computer science 、 Theoretical computer science 、 AND-OR-Invert 、 Optical computing 、 Pass transistor logic 、 CMOS 、 Three-input universal logic gate 、 Logic gate 、 Toffoli gate
摘要: In the recent scenario of microelectronic industry, reversible logic is considered as burgeonic technology for digital circuit designing. It deals with aim to generate circuits zero power loss characteristics. Optical computing, Nanotechnology, Low CMOS design and Digital Signal Processing DSP processors are leading areas development concept logic. Researchers have already proposed various subsystems computer creation low devices help numerous available gates. Here in this paper, authors a new gate named CDSM 4×4 size. This used optimized 4-bit binary comparator. The optimization improved compared existing designs based on some significant performance parameters such total number gates, garbage outputs generated, constant inputs quantum cost. Comparators widely computing applications counters, convertor, Central Unit CPU control etc. comparator using can be visualized subsystem systems.
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