The Molen compiler for reconfigurable processors

摘要: In this paper, we describe the compiler developed to target Molen reconfigurable processor and programming paradigm. The automatically generates optimized binary code for C applications, based on pragma annotation of executed hardware. For IBM PowerPC 405 included in Virtex II Pro platform FPGA, implemented generation, register, stack frame allocation following EABI (embedded application interface). backend has been extended generate appropriate instructions hardware data transfer, taking into account information specific implementations system. Starting with an annotated application, a complete design flow integrated executable bitstream processor. flexible proposed infrastructure allows consider special features architectures. order hide reconfiguration latencies, instruction-scheduling algorithm dynamic configuration instructions. schedules, advance, instructions, conflicts resources (FPGA area) between operations. To verify compiler, used multimedia video M-JPEG encoder which discrete cosine transform (DCTa) function was mapped FPGA. We obtained overall speedup 2.5 (about 84p efficiency over maximal theoretical 2.96). performance is achieved using generated nonoptimized DCTa implementation. tested DCT, quantization, VLC Based simulation results, determine that, while simple scheduling produces significant decrease, our contributes up 16x speedup.