A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits
作者： Ankur Kumar , R.K. Nagaria
DOI: 10.1016/J.VLSI.2018.07.004
关键词: Electrical engineering 、 NMOS logic 、 Comparator 、 Fan-in 、 PMOS logic 、 Leakage (electronics) 、 Domino 、 CMOS 、 Cascode 、 Computer science
摘要: Abstract A new leakage tolerant high speed domino gate having higher noise immunity, low power dissipation, and less process variations for wide fan-in OR logic is developed. This paper deals with the design of a comparator based that decides output on basis voltage difference across pull down network. In order to mirror comparator, PMOS replaced by NMOS variation. Furthermore, stacking accomplished reduce total current transfer in cascode fashion. Hence, proposed can be operated deep submicron regime. The simulation results confirm exhibits about 17.58% dissipation reduction 1.21 times immunity improvement contrast reported comparison domino. are achieved Cadence Virtuoso environment using SPECTRE simulator 45 nm CMOS technology.
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