Techniques to reduce transmitted jitter
作者： Casper Dietrich
DOI:
关键词: Matched filter 、 Phase-locked loop 、 Computer science 、 Clock domain crossing 、 Jitter 、 Signal 、 Electronic engineering 、 Signal transfer function 、 Clock signal 、 Self-clocking signal
摘要: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR receive an input signal suffers from jitter. generate matched having substantially the same as of signal. To signal, use provided by single side band oscillator, CMU, or level jitter to FIFO sample store such samples. CMU request output samples at frequency determined reference
lens.org 参考文章(26)
Bernard J. Rekiere, Satyan G. Pitroda, Line variation compensation system for synchronized pcm digital switching ,(1972)
Winston Mok, Ryan Richard Schatz, John Norman Walsh, Adaptive phase shift filtration of pointer justification jitter in synchronous-plesiosynchronous signal desynchronization ,(2000)
Ralph Urbansky, Circuit arrangement for bit rate adjustment ,(1992)
Sherre M. Staves, Ernest E. Bergmann, Digital phase locked loop clock recovery scheme ,(1987)
Scott Southwell, Benjamin Tang, Nicholas Robert Steffen, Pll/dll dual loop data synchronization utilizing a granular fifo fill level indicator ,(2001)
John R. Long, Digital phase aligner and method for its operation ,(1989)
G. Dehart Kenton, Ethernet device and method for extending ethernet fifo buffer ,(2002)
Myeon-Gyun Cho, Ho-Jin Kim, Communication system and method for increasing communication efficiency ,(2002)
Xicheng Jiang, Aaron W. Buchwald, Myles Wakayama, Howard A. Baumer, Avanindra Madisetti, Jurgen Van Engelen, Michael Le, Hui Wang, Phase interpolator device and method ,(2004)
Scott Southwell, Benjamim Tang, Nicholas Robert Steffen, PLL/DLL dual loop data synchronization ,(2001)