Completing high-quality global routes

摘要: To ensure chip manufacturability, all routes must be completed without violations. Furthermore, the chip's power consumption and performance are determined by length of its routed wires. Therefore, our work focuses on minimizing wirelength. Our key innovations include: (1) a novel branch-free representation (BFR) for nets, (2) trigonometric penalty function (TPF), (3) dynamic adjustment Lagrange multipliers (DALM), (4) cyclic net locking (CNL), (5) aggressive lower-bound estimates (ALBE) A*-search, resulting in faster routing. We complete routable ISPD 2008 contest benchmarks re-placed adaptec suite violation produce shorter routes.