An efficient retargetable framework for instruction-set simulation

摘要: Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity the architectures demands high performance simulation, variety available makes retargetability a critical feature instruction-set simulator. Retargetability requires generic models while target specific customizations. To address these contradictory requirements, we have developed instruction model decode algorithm that facilitates easy efficient ISA-simulator for wide range such as RISC, CISC, VLIW variable length set processors. The is used to generate compact debug descriptions very similar manual. These simulators. generation simulator completely separate from simulation engine. Hence, can incorporate any fast technique in our retargetable framework without loosing performance. We illustrate approach using two popular, yet different realistic architectures: Sparc ARM.