Peripheral interface circuit which snoops commands to determine when to perform DMA protocol translation

摘要: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its peripheral interface(s), using pipelined architecture to increase the use of available data transfer bandwidth. To accomplish above, LBPI, which is coupled between provided includes Read Ahead Buffer, Counter, Data Out Latch, Controlling State Machine with Configuration Register. In one embodiment, LBPI can be selectably configured couple on host side either VL or PCI bus. Efficiency Read-Ahead operations further enhanced by maintaining countdown number words sector already transferred and/or "snooping" device commands from intelligently predict occurrence subsequent read transfers commands. The also "snoops" maintain record operating parameters devices keeps track currently active. supports DMA PIO side. another translates memory into IO improve efficiency transfers. Timeout Counter used during mode prevent system indefinitely waiting an appropriate Request Signal selected peripheral. During operation, forced interrupts may generated transmitted in order emulate operation. imposed status "Fake 3F6" register utilized transmit information system.