作者: Rung-Bin Lin , Shu-Yu Chen
DOI: 10.1016/J.INS.2007.01.013
关键词: Strength of a graph 、 Moral graph 、 Algorithm 、 Mathematical optimization 、 Constrained optimization 、 Graph theory 、 Simulated annealing 、 Integer programming 、 Graph bandwidth 、 Graph coloring 、 Mathematics
摘要: A graph model for describing the relationships among wire segments is crucial to constrained via minimization (CVM) in a VLSI design. In this paper we present new model, called conjugate conflict continuation graph, multi-layer CVM with stacked vias. This eases handling of problems. An integer linear programming (ILP) formulation and simulated annealing (SA) algorithm based on are developed solve CVM. The ILP too complicated efficiently. SA average achieves 6.4% reduction layouts obtained using commercial tool under set practical constraints which metal wires (including pins) used cell layouts, power rails rings, clock routing treated as obstacles or fixed-layer objects