A highly regular and scalable AES hardware architecture
作者： S. Mangard , M. Aigner , S. Dominikus
关键词: Very-large-scale integration 、 CMOS 、 Encryption 、 Hardware architecture 、 Implementation 、 Scalability 、 AES implementations 、 Design flow 、 Key size 、 Computer science 、 Embedded system 、 Throughput (business)
摘要: This article presents a highly regular and scalable AES hardware architecture, suited for full-custom as well semicustom design flows. Contrary to other publications, complete architecture (even including CBC mode) that is in terms of throughput the used key size described. Similarities encryption decryption are utilized provide high level performance using only relatively small area (10,799 gate equivalents standard configuration). reached by balancing combinational paths design. No published provides similar or comparable regularity. Implementations fastest configuration 241 Mbits/sec on 0.6 /spl mu/m CMOS process cells.
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