A 40K cache memory and memory management unit
作者： J. Cho , Jin Kaku
DOI: 10.1109/ISSCC.1986.1156968
关键词: Uniform memory access 、 Interleaved memory 、 Cache-only memory architecture 、 Registered memory 、 Memory management unit 、 Non-volatile random-access memory 、 Embedded system 、 Conventional memory 、 Cache coloring 、 Computer data storage 、 Computer science 、 Shared memory 、 Auxiliary memory 、 Memory management 、 Computer memory 、 Memory refresh 、 Non-uniform memory access 、 Random access memory 、 CPU cache 、 Flat memory model 、 Cache pollution 、 Computer hardware 、 Semiconductor memory 、 Memory map
摘要: The development of a cache memory to support 32b microprocessors will be offered. Including an on-chip unit the circuit operates at 33MHz, delivers data CPU in 2/4 clock cycles and is fabricated 2μm CMOS.
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