MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelines

摘要: A new asynchronous pipeline design is introduced for high-speed applications. The uses simple transparent latches in its datapath, and small latch controllers consisting of only a single gate per stage. This stage structure combined with an efficient transition-signaling protocol between stages. Initial pre-layout HSPICE simulations 10-stage FIFO on 16-bit wide datapath indicate throughput 3.51 GigaHertz 0.25 /spl mu/ CMOS, using conservative process. performance competitive even that wave pipelines, without the accompanying problems complex timing much effort. Additionally, gracefully robustly adapts to variable-speed environments. implementations are extended fork join structures, handle more system architectures.