Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits

摘要: A base cell for a gate array or standard integrated circuit design has N and P wells organized in checkerboard fashion, each well containing several devices respectively. first of the plurality relatively deep regions is adjacent to at least second regions. The region along edge region, region. edges are perpendicular. An cells therefore pattern, unlike striped pattern typical designs. amenable minimizing clock parasitic capacitance when clocked inverters, including complimentary inverters latches, laid out vertexes pattern.