Logic macro and protocol for reduced power consumption during idle state
作者： Dac C. Pham , Jonathan H. Raymond , Sebastian T. Ventrone
DOI:
关键词: Electronic circuit 、 Electrical engineering 、 Programmable logic array 、 Logic optimization 、 Sequential logic 、 Integrated circuit 、 Logic family 、 Electronic engineering 、 Logic gate 、 Pass transistor logic 、 Engineering
摘要: A control circuit and protocol are disclosed for an integrated (such as a static PLA) wherein standby power is minimized during idle processor state condition without loss of outputs. For PLAs, circuits shutoff any active current path drive the logic array outputs to zero whenever exists. Inputs held in latches associated with PLA. The novel halt includes: powering-down macro upon initiation by halting all internal clocks then decoupling from supply voltage VDD. Circuit power-up includes reactivating first coupling VDD allowing sufficient time stabilize; restarting previously halted clocks. Analogous techniques also described dynamic PLAs.
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