Optimization circuitry and control for a synchronous memory device with programmable latency period

摘要: A method and apparatus for optimizing the speed path of a memory access operation in synchronous depending upon present latency period DRAM. The improved device compensates time between row address latching column tRCD by delaying presentment to compensate from available valid data-out (tAA) when is critical parameter. Optimization circuitry reduces amount tAA 'shifts' it more parameter tRCD, enabling optimization or reduction allocated compensating with extra tAA. Thus, enables an optmization total optimized