Architecture and applications of the HiPAR video signal processor

摘要: We propose the architecture of a highly parallel DSP (HiPAR-DSP) as flexible and programmable processor for image video processing. The design is based on an analysis processing algorithms in terms available parallelization resources, demands program control, required data access mechanisms. This led to very long instruction word (VLIW)-controlled ASIMD RISC-architecture with four or sixteen paths, employing data-level parallelism, instructions, micro-instruction pipelining, transfer concurrently Common patterns are supported by use shared on-chip memory matrix type separate data-cache per path. By properly balancing controlling capabilities internal external bandwidth, this approach optimized make best currently silicon resources. A high clock frequency achieved implementation classic RISC features. fully supports level language programming. With 16 path version 100 MHz clock, sustained performance more than 2 billion arithmetic operations second (GOPS) wide range algorithms. examples show like histogramming, Hough transform, search sorted list efficient prototype paths available, using 0.6 /spl mu/m CMOS technology.