Local clock skew minimization using blockage-aware mixed tree-mesh clock network

摘要: Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation of most important objectives during synthesis. Local (LCS) between any two sinks with distance less than or equal to a given threshold. It defined ISPD 2010 High Performance Network Synthesis Contest [1], and it novel criterion that captures process effects on network. In this paper, we propose hybrid method creates mesh upon tree topology. Total wire buffer capacitance minimized under LCS slew constraints. our method, will be built first according positions sinks. A top-level then drive mesh. blockage-aware routing used construction. Experimental results show efficiency solution generated by approach can satisfy constraint all benchmarks contest fair usage.