Task selection for a multiscalar processor

摘要: The multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without impeding improvements clock speeds. main goal this paper is understand the key implications architectural features for compiler task selection from point view performance. We identify fundamental performance issues be: control flow speculation, data communication, dependence load imbalance, overhead. show that these are intimately related few characteristics tasks: size, inter-task flow, dependence. describe heuristics select tasks with favorable characteristics. report experimental results successful boosting overall by establishing larger ILP windows.