The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems

摘要: ExaNest is one of three European projects that support a ground-breaking computing architecture for exascale-class systems built upon power-efficient 64-bit ARM processors. This group share an "everything-close" and "share-anything" paradigm, which trims down the power consumption -- by shortening distance signals most data transfers as well cost footprint area installation reducing number devices needed to meet performance targets. In ExaNeSt, we will design implement: (i) physical rack prototype its liquid-cooling subsystem providing ultra-dense compute packaging, (ii) storage with distributed (in-node) non-volatile memory (NVM) devices, (iii) unified, low-latency interconnect, designed efficiently uphold desired Quality-of-Service guarantees mix inter-processor flows, (iv) efficient rack-level sharing, where each page cacheable at only single node. Our target test alternative interconnect options on actual hardware, using real-world HPC applications. The ExaNeSt consortium brings together technology, skills, knowledge across entire value chain, from IP, system deployment, all way up operating systems, storage, HPC, big frameworks, cutting-edge