Embedded DRAM cache memory and method having reduced latency
作者： Joseph Jeddeloh
DOI:
关键词: Computer hardware 、 Cache coloring 、 Cache pollution 、 Pipeline burst cache 、 Cache-only memory architecture 、 Uniform memory access 、 Computer science 、 Non-uniform memory access 、 Memory controller 、 Registered memory
摘要: A computer system includes a processor, memory, and an integrated circuit controller coupled to the processor memory. The memory interface embedded cache with interface. at least one DRAM array, tag controller. initiates access either or both array as well before has determined if will result in hit miss. If determines that hit, data are from processor. miss,
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