Creating an Agile Hardware Design Flow

摘要: Although an agile approach is standard for software design, how to properly adapt this method hardware still open question. This work addresses question while building a system on chip (SoC) with specialized accelerators. Rather than using traditional waterfall design flow, which starts by studying the application be accelerated, we begin constructing complete flow from expressed in high-level domain-specific language (DSL), our case Halide, generic coarse-grained reconfigurable array (CGRA). As under-standing of grows, CGRA evolves, and have developed suite tools that tune code, compiler, increase efficiency resulting implementation. To meet continued need update parts maintaining end-to-end created DSL-based generators not only provide Verilog needed implementation CGRA, but also create collateral compiler/mapper/place route needs configure its operation. provides systematic desiging evolving high-performance energy-efficient hardware-software systems any domain.