Variable delay line phase-locked loop circuit synchronization system
作者： Edwin L. Hudson , Mark G. Johnson
DOI:
关键词: Coprocessor 、 Computer hardware 、 CPU multiplier 、 CPU time 、 Central processing unit 、 Synchronizing 、 Computer science 、 Line (electrical engineering) 、 Clock signal 、 CPU core voltage
摘要: A system for synchronizing the operation of a CPU and coprocessor operating from common clock signal includes first voltage controlled delay line connected to receive it by fixed time interval before supplying one or coprocessor. second is an adjustable other The determined potential control generated phase locked loop circuit coupled output terminals
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