Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS
作者： P.V. Argade
DOI: 10.1109/43.21816
关键词: Skew 、 Iterative method 、 Inverter 、 Distortion 、 Advice (complexity) 、 Power factor 、 CPU time 、 Computer science 、 Capacitance 、 Transistor 、 Control theory 、 CMOS
摘要: A general procedure to size an inverter which drives a given capacitance load and has precise pull-up pull-down delays is discussed. This iterative combination of Newton-Raphson numerical method used the transistors, ADVICE simulations extract parameters in delay model for inverter. The makes it possible satisfy constraints precisely, while ensure accuracy. device-sizing then determine sizes inverters two paths, one consisting other three, each driving arbitrary capacitive load, such that complementary output paths minimal skew pulsewidth distortion irrespective processing variations. fully automatic achieve this requires only four takes about minutes CPU time on AMDAHL-5870 computer. circuit designed by also very small with temperature variation V/sub DD/ variation, input rise fall-time >
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