Improving IPS by network processors

摘要: Many present applications usually require high communication throughputs. Multiprocessor nodes and multicore architectures, as well programmable NICs (Network Interface Cards) provide new opportunities to take advantage of the available multigigabits per second link bandwidths. Nevertheless, achieve adequate performance levels efficient parallel processing network tasks interfaces should be considered. In this paper, we leverage processors heterogeneous microarchitectures with several cores that implement multithreading are suited for packet processing, investigate on use accelerate interface, thus developed above it. More specifically, have implemented an intrusion prevention system (IPS) such a processor. We describe IPS after its offloaded implementation allows faster both normal corrupted traffic. The benefits from placing close network, by using specialized processors, give many times lower latency higher bandwidth legitimate