Approach for routing an integrated circuit

作者: David C. Chapman

DOI:

关键词: Enhanced Interior Gateway Routing ProtocolEngineeringZone Routing ProtocolPolicy-based routingLink-state routing protocolMultipath routingEqual-cost multi-path routingDistributed computingDynamic Source RoutingStatic routing

摘要: A computer-implemented approach for routing an integrated circuit using non-orthogonal is accomplished during two phases: a global phase and detailed phase. During routing, indicators, in the form of hint polygons, are added to layout strategy lists, that include bias directions straying limits, generated new wires be added. The polygons lists used aid placing wires. If obstacle conflicts or insufficient space problems prevent wire, then resolution portion resolve conflict and/or provide additional route Obstacle includes, without limitation, moving changing geometry, add by direction adjusting inserting one more layer changes, instructing router backup insert bend, ripping-up rerouting wires, wire from destination connection point. Also, tight may employed accommodate constructing paths areas. Object specific design rule checks increase flexibility optimize performance. “On-the-fly” performed on portions as being constructed.

参考文章(25)
Jacob Greidinger, Mark R. Hartoog, Prasad Sakhamuri, Christine Fawcett, Eugenia Gelfund, Ara Markosian, Method for automatically routing circuits of very large scale integration (VLSI) ,(1995)
Fumihiro Minami, Midori Takano, Mutsunori Igarashi, Layout method of wiring pattern for semiconductor integrated circuit ,(1997)
Fumihiro Minami, Masako Murofushi, Layout design method and system for an improved place and route ,(1998)
Stacy W. Mehranfar, Richard J. Burns, Technology independent integrated circuit mask artwork generator ,(1990)
J. Scheible, T. Adler, An interactive router for analog IC design design, automation, and test in europe. pp. 414- 421 ,(1998) , 10.5555/368058.368253
E. Malavasi, A. Sangiovanni-Vincentelli, Area routing for analog layout IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 12, pp. 1186- 1197 ,(1993) , 10.1109/43.238611