Analyzing path delays for accelerated testing of logic chips
作者： Emily Ray , Barry Linder , Raphael Robertazzi , Kevin Stawiasz , Alan Weger
DOI: 10.1109/IRPS.2015.7112764
关键词: Transistor 、 Acceleration 、 Degradation (telecommunications) 、 Electronic engineering 、 Path (graph theory) 、 Test method 、 Engineering 、 Voltage 、 Stress (mechanics) 、 Electronic circuit
摘要: We develop a test methodology utilizing the critical path delay to monitor and predict degradation of circuits during ramp voltage stress (RVS). Stress is applied by looping functional patterns RVS. Our results demonstrate that behavior circuit can be characterized analyzed with RVS in manner similar developed for single transistor. This alternative fast lends itself in-line testing reduced times small sample numbers.
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