Modular exponentiation using parallel multipliers
作者： S.H. Tang , K.S. Tsui , P.H.W. Leong
关键词: Carry (arithmetic) 、 Public-key cryptography 、 Field-programmable gate array 、 Chinese remainder theorem 、 Modular exponentiation 、 Computer science 、 Computer hardware 、 Fpga architecture 、 Scheme (programming language) 、 Public key cryptosystem
摘要: A field programmable gate array (FPGA) semi-systolic implementation of a modular exponentiation unit, suitable for use in implementing the RSA public key cryptosystem is presented. The design carefully matched with features FPGA architecture, utilizing embedded 18/spl times/18-bit multipliers on and employing carry save addition scheme. Using this 1024-bit can operate at 90 MHz Xilinx XC2V3000-6 device perform decryption 0.66 ms Chinese Remainder Theorem.
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